This invention relates to configurable logic elements and arrays of configurable logic elements. More particularly, this invention relates to configurable logic elements that are capable of logic operations, arithmetic operations and data storage.
Since the introduction of electronic computing, the trend has been toward decreased use of hard-wired logic in favor of electronically programmable systems. Example milestones include stored program control computers, programmed memory management arrangements, programmable input/output controllers, intelligent terminals and modems. In recent years, the very definitions of hardware/firmware/software have become blurred with the development of EEPROM (Electrically Erasable Programmable Read Only Memory) and PAL (Programmable Array Logic) elements, which are hardware devices that can be modified under software control. Each of these steps has allowed more of the functionality of greater numbers of subsystems to be altered by software, but the connection among the subsystems has remained largely fixed. As the evolution continues, the interconnectivity of these subsystems is also made programmable, thus expanding the size of systems that can be programmed in great detail.
In U.S. Pat. No. 4,706,216 issued Nov. 10, 1987, a configurable logic element is described. That logic element is embedded in a configurable routing fabric that allows many different interconnections of the embedded configurable logic elements. In connection with the routing fabric, the term "configurable" means that a plurality of buses are provided, with switches arranged to connect one bus to another under control of a signal derived from a control bit stored in association with the routing fabric. From time to time, the information in the control bits may be changed (for example, when the designer choses to try a different interconnection pattern) and thereby the interconnection of the routing paths is changed and the functionality of the entire arrangement is altered. In connection with the logic elements, the term "configurable" means that control bits are included in the element and those control bits dictate which of a plurality of logic functions are carried out by the logic element. The general structure of each of the configurable logic elements in the '216 patent, together with a portion of the configurable routing network that is closely associated with the logic elements, is depicted in FIG. 1 (which is a combination of FIGS. 7 and 8 of the '216 patent).
In FIG. 1, selector 10 is the configurable routing network portion. It includes four direct inputs (A, B, C and D) and a feedback input. Under configuration control bits (not shown), selector 10 outputs one signal set on bus 11 and another signal set on bus 12. The two signal sets are applied to an arithmetic/logic unit 15 which develops two outputs on leads 13 and 14. Those two outputs as well as the A lead input are applied to a selector circuit 16. Selector 16 has two outputs which are applied to selector circuit 17. One of the outputs of selector circuit 16 is also applied to a latch circuit 18 whose output is applied to selector circuit 17. Selector 17 develops the feedback input and two outputs (X and Y) of the configurable logic element. Thus, from the viewpoint of overall functionality, the configurable logic element of the '216 patent develops two output signals in response to four input signals.
The arithmetic/logic element 15 comprises two 8-bit RAMs (FIG. 8 in the patent). Each is responsive in effect, to a 3-bit address. The contents of the memory (which are loaded at configuration time) dictates the logic function that the unit performs. No means are provided for modifying the contents of those memories during operation. Also, aside from the latch at the output of selector 16, no read/write memory is available in the unit. This is a substantial disadvantage of the unit because in many applications a need exists for buffering data that is generated by one or more of the configurable elements in the configurable arrangement, or array, that is made up of those units. Additionally, the device described in the '216 patent is not well suited for arithmetic functions such as addition or subtraction. First, such operations require 2N+1 inputs, where N is an integer, and the '216 device had only four inputs, which does not satisfy the 2N+1 requirement. Secondly, and more importantly, the interconnection structure within the device provides for no direct connectivity between the two 8-bit RAMs (the function defining elements), which substantially limits the functional flexibility of the device in connection with arithmetic operations.